product brief april 2000 1 3 celxpres ? t8206 asynchronous transfer mode (atm) interconnect features n utopia cell-level handshake interface (atm or phy layers) n multi-phy (mphy) operation n programmable atm layer supports up to 16 phy ports n egress sdram buffer support to extend utopia output priority queues for 32k to 512k cells: 32 queues configurable up to four queues per phy with programmable sizes programmable number of utopia output queues with four levels of priority n support of atm traffic management via partial packet discard (ppd), forward explicit congestion notification (fecn), and the cell loss priority (clp) bit n controlled slew rate gtl+ i/o: programmable as bus arbiter >1.5 gbit/s cell bus operation n flexible per virtual channel (vc) cell counters n cell header insertion with virtual path identifier (vpi) and virtual channel identifier (vci) translation via external sram (up to 64k entries) n support of network node interface (nni) and user network interface (uni) header types with optional generic flow control (gfc) insertion n programmable operations and maintenance and resource management (oam/rm) cell routing n support of multicast and broadcast addresses per phy n optional monitoring of misrouted cells n microprocessor interface, supporting both motor- ola * and intel ? modes (multiplexed and nonmulti- plexed) n control cell transmission and reception through microprocessor port n eight gpio pins n jtag support n compatible with tr a n sw i t c h cellbus ? n seamlessly extends wildwire ? central-site family to the backplane n single 3.3 v power supply n 3.3 v ttl i/o (5 v tolerant) n 272-pin plastic ball grid array (pbga) package n industrial temperature range (C40 c to +85 c) applications n asymmetric digital subscriber line (adsl) digital subscriber line access multiplexers (dslams) n access gateways n access multiplexers/concentrators n multiservice platforms description the celxpres t8206 device meets the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications for cell-level handshake and mphy data path operation. the t8206 supports mphy operation with one transmit cell available (txclav) signal and one receive cell available (rxclav) signal for up to 16 phy ports. in addition to the required utopia signals, the optional transmit parity (txprty) and receive parity (rxprty) signals are provided. * motorola is a registered trademark of motorola, inc. ? intel is a registered trademark of intel corporation. ? transwitch and cellbus are registered trademark of transwitch corp.
2 lucent technologies inc. celxpres t8206 product brief asynchronous transfer mode (atm) interconnect april 2000 3 description (continued) the celxpres t8206 device integrates all of the required functionality to transport atm cells across a backplane architecture with high-speed cell traffic exceeding 1.5 gbits/s to a maximum of 32 destinations. the management of multiple service classes and monitoring of performance on atm and phy interfaces is incorporated in the devices functionality. traffic delivery to multi-phys (mphys) is managed through the utopia interface. the t8206 may be configured as an atm or phy level device providing cell routing between utopia and a 32-bit wide cell bus. in addition to the 32 data signals, the bus has the following signals: n read clock n write clock n frame sync n acknowledge atm cells arriving at the utopia receive interface may get vpi and vci translation and routing information from a look-up table in external sram. an external synchronous dynamic random access memory (sdram) is used to extend the buffering for atm cells destined for the utopia transmit interface. this external sdram may be parti- tioned into four or less independently sized queues per phy. the four queues may be used to implement quality of service (qos) using different priorities for each queue. the celxpres t8206 provides a shared utopia mode, which allows two devices on different cell buses to share the same utopia bus in atm mode. using a glueless interface, the two t8206 devices resolve queue priorities and arbitrate the use of the utopia bus. this shared mode can be used to provide redundancy or increase the system capacity. in addition, an external microprocessor may send or receive control or loopback cells through the microprocessor interface. the 8-bit microprocessor interface may be configured to be motorola or intel compatible and is used to configure and monitor the device.
product brief celxpres t8206 april 2000 asynchronous transfer mode (atm) interconnect lucent technologies inc. 3 1 3 description (continued) 5-7542.r1 figure 1. functional block diagram one or two 32k to 256k x 8 look-up engine rx utopia interface rx phy fifo (16 cells) control cell tx fifo (1 cell) loopback fifo (1 cell) control cell rx fifo (16 cells) tx phy fifo (128 cells) sdram interface tx utopia 1m to 16m x 16 sdram microprocessor interface micro- processor cell bus cell bus arbiter cell bus monitoring cell bus interface cell bus tx utopia interface rx utopia tx utopia (4 cells) input fifo (64 cells) cell buffer (lut) srams rx utopia fifo
3 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. wildwire and celxpres are trademarks of lucent technologies, inc. copyright ? 2000 lucent technologies inc. all rights reserved april 2000 pb00-008dlc (replaces pn00-065dlc) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) celxpres t8206 product brief asynchronous transfer mode (atm) interconnect april 2000 description (continued) figure 2 illustrates the use of the celxpres t8206 in a system with dual backplane cell buses using shared uto- pia mode. in this configuration, both t8206 devices on each card receive cells from the utopia bus, and each device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. in the egress direction, each t8206 device receives cells from its cell bus to transmit on the utopia bus. queue priori- ties are resolved using a two-wire interface between the two devices. although a single atm virtual connection cannot use both backplane cell buses simultaneously, no restrictions exist for a single phy utilizing both back- plane cell buses for different virtual connections. in the event of a bus failure, the t8206 devices may be config- ured for one device to assume bus responsibility from the other. figure 2. dual bus implementation upstream translation downstream buffering t8206 downstream buffering t8206 upstream translation backplane bus upstream translation downstream buffering t8206 downstream buffering utopia upstream translation xdsl dsp xdsl dsp xdsl dsp utopia phys backplane bus xdsl dsp xdsl dsp xdsl dsp xdsl dsp xdsl dsp utopia phys t8206
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